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hi. I did't the entire code, I just said about a part that's my problem.
entire code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
use ieee.numeric_std.all;
use work.asci_types.all;
entity rez is
port (
CLK_20M : in STD_LOGIC...
hi dears. the following code has result in isim, but on fpga board doesn't work. would you help me?
vhdl code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
use ieee.numeric_std.all;
entity rez is
port (
CLK_20M : in STD_LOGIC;
);
end rez...
hi dear friend. I used your advises and wrote the following code. in simulation ,when I use "std_logic_vector (25 downto0 )" instead of "integer range " for "c" and "counter_2" , the result for "c" is "xxxxxxxxxxxxxxxxxxxxxx"! what's should I do? thank you in advanced.
simulation is in ise...
Hi, dear friends. Maybe I didn’t explain enough at #6.
My problem: I have to counting a clock (that is unknown period and frequency) in just 1 second.
When I use another clock (like 20 MHz) to create 1 second, I faced to this error in ISE :
“Xst:1534 - Sequential logic for node <a> appears to...
Hi, it's simple code for 1 digit diplay 7-seg.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
entity seg is
port (
SS2_A,SS2_B,SS2_C,SS2_D,SS2_E,SS2_F,SS2_G : out std_logic;
SS1_A,SS1_B,SS1_C,SS1_D,SS1_E,SS1_F,SS1_G : out std_logic...
hi, I have this problem,too. I need to use encoder H_sense A and/or B to calculate speed of dc motor with vhdl. the way of calculation is not impoprtant. I use fpga board spartan 3. internal clock is 20 MHz and motor fed with 3.3 volt voltage.
hi, i face to a problem when compiling below code in ise.
would you help me?
error is : Line 17. conv_integer can not have such operands in this context.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity dc1 is
port (
in1 : in...
hi ads-ee! As you said I changed variables to signals, but simulation could not be complete!! I faced to this message "ERROR: In process dc1.vhd:div_3
Target Size 20 and source size 21 for array dimension 0 does not match."
and the quotient is not correct yet!
library ieee;
use...
hi again! I write this code for binary divisiona and value dividend and divisor. after simulation in ISE the quotient was wrong. would you help me wha's wrong with this code? thank you.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_unSIGNED.ALL;
use ieee.numeric_std.all;
use...
hi ads-ee. thanks for your attention.
actually in this code in want to count number of ENCODER_HALLSENSOR_B's pulses in 1 second.
I used the rising edge of CLK_20M (20 MHz) to counting 0 to 20 millions to create one second and at this time I used another counter (count) to counting...
hi, in part of my project I have to divide a 26 bit binary variable to 19 bit binary constant. would you help me? language is vhdl. thank you in advanced.
it's my code and doesn't work!
process (CLK_20M)
constant a : std_logic := "1000111101110000000"; --293760
variable counter...
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