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Recent content by salma shabayek

  1. S

    OOK/ASK Modulation on ADS Agilent

    hey all, Im still new to ADS agilent and I need to generate an OOK modulated signal with a data rate of 10kbps and an rf carrier of 2GHz. Can anyone help? Thanks alot
  2. S

    rf frequency downconverter mixer in simulink

    Hey all, I'm trying to model a frequency downconverter mixer on simulink. The input is 2Ghz mixed with LO=1.96G. the sample time i put is 0.01e-9 and the solver with a fixed step. unfortunately the output frequency is the same as the input frequency. I attached the model. Can anyone help? Thanks
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    verilog model of spi flash memory needed

    hi all, I designed an SPI interface and want to integrate an spi flash memory to it.Actually I’m a bit confused about something All the memories I find with the needed specs (16Mbits, 100Mhz) have 24 bits address space but organized in 8 bits address The 24 bits address space is designed to...
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    the propagation delay of the pseudo nmos inverter

    pseudo nmos inverters Dear all, Im supposed to calculate the propagation delay of the pseudo nmos inverter i found these 2 rules: tplh=(1.7*C)/(Kp*VDD) tphl=(1.7*C)/(kn*(1-0.46/r)*VDD) are these 2 rules right? and if yes . from where did they come?? and also how do i get the Vol? Thanks
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    why does NMOS pass a strong logic 0 and a weak logic 1

    attached is a lecture explaining it very wel with examples
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    designing a 4 bit counter

    my only constraint is that the counter consists of 4 d flip flops and any 3 logic gates I will try to implement it to count to 1100 as you told me I hope it works Thanks alot :-) Added after 45 minutes: I am really sorry but can a counter count only even numbers?? I am really sorry for...
  7. S

    designing a 4 bit counter

    Thanks alot But what if I am constrained with 4 flipflops and only 3 logic gates Do you have any idea how this will work?? Will it contain some sort of special feature ? Thanks alot again
  8. S

    designing a 4 bit counter

    how do i design a 4 bit counter using d flip flops thanks
  9. S

    determinig the configuration bits of the FPGA

    Yep, :) I do go to a very interesting uni
  10. S

    determinig the configuration bits of the FPGA

    Dear all, I am having problems solving that question: An FPGA has an array of 128 X 128 logic elements (LEs) like the one shown below, each with five inputs and one output. There are 129 vertical and 129 horizontal routing channels with four segmented wires (single length) and two long wires...
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    Transistor layout using mentor tools

    Hey guys, I am new to layout and I'm using the mentor tools to make te layout of an inverter. I am not using any models for the transistors so Ill be drawing them from scratch. Does anyone have a basic tutorial that can help me with that??? Thanks alot
  12. S

    simulating on mentor graphics tools

    Dear all, I'm using the mentor grahics tool fot designing an inverter and the following errors comes up to me each time ERROR 1577: In file "./1st-inverter-testbench_default.spi" line 19: + OBJECT "X_1ST-INVERTER-TRIAL1.MS2": Model 1ST-INVERTER-TRIAL.PCH not yet defined. ERROR 1577: In file...
  13. S

    Differential dynamic comparator - latch comparator problem

    latch comparator problem i am trying to simulate a fully differential dynamic comparator in 0.13um process, vdd=1.2v, when the threshold is zero i have only one error when the ramp is falling below the zero( threshold) attached is my simulation ; the ramp is the positive input,the purple line...
  14. S

    replacing an ideal tail current in a differential pair

    Than you alooott.... but there is one thing not yet clear.. im using 0.13u technology yes with vdd=1.2v and while using the gm/id method to size the transistors i get W/L < 1..is that acceptable?? will it keep the transistors in saturation or will it move them to linear?? Thanks aloot guysss
  15. S

    replacing an ideal tail current in a differential pair

    replacing a differential Dear all, I'm having a trouble in replacing the ideal tail current in the differential pair with an nmos current sourc transistors mirrored to an nmos diode connected transistor. I did so by placing the nmos transistor with double the size of the nmos input transistor...
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