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Recent content by salma ali bakr

  1. salma ali bakr

    wireless sensor networks newbie

    Hello, I would like to attach some WSN to devices to collect info about power usage.. but I haven't worked with WSN.. so how should I start and how much time will it take me to actually start working in hardware with such sensors ... I hope it doesn't take too long cause my project has other...
  2. salma ali bakr

    Help me with doing a simple energy management algorithm

    Hello, I would like to do a simple energy management algorithm.. do you suggest using simulink then doing hardware in the loop or going directly to programming a microcontroller using C? Thanks!
  3. salma ali bakr

    Heat Exchanger vs. Heat Retriever

    Hello, I'd like to know the difference between a heat exchanger and a heat retriever, if any... Thanks :)
  4. salma ali bakr

    FPGA, CPLD in Egypt ?!

    A friend who did an internship there a while back, almost 5 or 6 years ago. I'll give you his contact inshaAlllah, to know more about this company :)
  5. salma ali bakr

    A good book about Photovoltaics??

    Hello, I'd like to find a good book that talks about photovoltaics please...a book that mixes between the theoretical as well as the practical side of photovoltaics... Thanks in advance :-D
  6. salma ali bakr

    low power design in UPF

    **broken link removed** Here's a really good guide to get you started. It has some examples codes and a checklist as well. Enjoy!
  7. salma ali bakr

    related to gate level simulation

    GLS is similar to RTL simulations...what is extra in it is just the gates delays...You gotta learn functional verification for both :D
  8. salma ali bakr

    combinational circuit design:RTL to GDSII

    for constraining combinatorial logic, you don't need to associate input and output delays with a clock....it's the opposite of constraining sequential logic, where you always need to link your block with a clock
  9. salma ali bakr

    Formality warnings - Cannot link cell

    You can enter the design in three forms: VHDL/Verilog, DB, or EDIF And the design libraries in DB If you're using the GUI, then you'll find this in the tabs used for reading the design and libraries....if you're using commands then find the necessary command, I don't know it by heart
  10. salma ali bakr

    Which PhD offer is better? Plse help me...

    KULeuven has a high worldwide ranking. I guess it's number 50. IMEC is Europe's largest independent research center in Micro and Nano Technologies. So just go to Belgium and enjoy lots of chocolates and waffles :D
  11. salma ali bakr

    Formality warnings - Cannot link cell

    make sure you choose the correct DB file for your library
  12. salma ali bakr

    What will be the future of VLSI Engineers?

    Re: FUTURE VLSI ? I believe that as long as we're living and not retired from work, VLSI will exist but the technologies used will vary till scaling reaches saturation! After I'm 60 years old I won't care about working anymore...Maybe before that even :)
  13. salma ali bakr

    problem about Synthesis

    you should constrain your design according to its surrounding environment...so you should see where your inputs are coming from and where your outputs are going to be able to constrain your ports...this includes the clock signals and their uncertainty :)
  14. salma ali bakr

    STA in asynchronous circuits

    http://www-classes.usc.edu/engr/ee-s/552/ieee-asyntutorial.pdf **broken link removed**
  15. salma ali bakr

    which tool can generate a sdc file

    Design Compiler generates SDC files (Synopsys Design Constraints)

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