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Recent content by Salil Vaidya

  1. S

    how to combine outputs???

    because if i take them as a bus and write my code...it shows me warning for each product term...
  2. S

    how to combine outputs???

    If i have p0,p1,p2.......p15 as separate 1 bit outputs,thencan i make a 16 bit bus [15:0] using all these individua outputs??? I m making a 8*8 wallace multiplier and i want to combine all these 1 bit outputs to make a 16 bit output.how to do that???
  3. S

    ALU design in VERILOG

    i got it.bt can you please post some example plz.....
  4. S

    ALU design in VERILOG

    Plz help.i need to get this done.
  5. S

    ALU design in VERILOG

    thanks rohit.actually this was given to me as home assignment.bt in the instructions to solve the assignment,it was given that you should make all the individual modules first and then use them in your design.so,thats why i thot if it said so in the instructions,how can it be so simple???because...
  6. S

    ALU design in VERILOG

    my ALU is has 3 select lines.it will take 2 inputs a and b.according to select line inputs,it has to do a=b,a-b,a and b,etc. so,i have made separate modules for adder,subtractor,and gate,shift left,etc. so, basically now i will have to build a mux which will select one of these operations.bt,i m...
  7. S

    ALU design in VERILOG

    rohit,dats what i have done in my adder code.i know how to call another module.bt if i hve to call smthng inside a case statement,how do i do it???
  8. S

    ALU design in VERILOG

    can you please tell me syntax or post an example???
  9. S

    ALU design in VERILOG

    this is code of my 8bit adder which i made instantiating 1 bit adder: module adder8bit( input [7:0] a, input [7:0] b, input cin, output [7:0] sum, output cout ); wire w1,w2,w3,w4,w5,w6,w7; adder1bit fa1(a[0],b[0],cin,sum[0],w1); adder1bit...
  10. S

    ALU design in VERILOG

    ohk..so shld i declare it as wire before case statement...n use dat wire inside tha case? - - - Updated - - - plz can u post the syntax??? basically,i will have to prepare a mux using case statement right???So,when i do it,for a particular combination of select lines, say for 000,my...
  11. S

    ALU design in VERILOG

    yes...i used case statement.bt how do i instantiate the modules inside case statement??? - - - Updated - - - mrflibble ...i understand what you are saying...i also knw how to write case statement.bt my prob is inside case,i will hve to instantiate my individual modules ryt???how to do that...
  12. S

    ALU design in VERILOG

    Because I tested all the individual modules by writing testbench.They are working fine.The problem i have is that how do i connect these modules to mu ALU???Baecause,my ALU should select the functionality of any 1 of these modules according to select line inputs...plz help - - - Updated - - -...
  13. S

    ALU design in VERILOG

    I am making a 8-bit ALU using verilog. I have made all the modules and they are working separately. like an adder,subtractor,left shift,etc. But, now i have to combine them in my ALU. How can I do this??? If I make a mux, then how to connect all these separate modules to the mux??? plz help....
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