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Recent content by sakthi_s

  1. S

    Max no. of files that can be opened

    Does anyone have know whether there is any limitations on the no. of files that can be opened at a time with vcs? Thanks
  2. S

    edge triggered and level triggered interrputs

    Search this forum for similar topic posted 2-3 weeks ago..
  3. S

    Question about c model for verification.

    If you are using vcs (7 and above??) you can use directC interface. It's similar to PLIs - you can call C functions from verilog. But if your C code has to be portable across different simulators then PLI is better I guess as directC is only supported by Synopsis.
  4. S

    Performance modeling with C/C++

    Performance modeling Hi Everyone, I have seen c/c++ used widely for this, but anyone want to add anything to this list and why?? Thanks
  5. S

    Level vs. Edge Sensitive Interrupts

    edge triggered vs level trigger Here is an artcile that I had bookmarked, may this will help you: https://www.qnx.com/developers/docs/qnx_6.1_docs/neutrino/prog/inthandler.html
  6. S

    Which Verilog PLI book is better, Sutherland or Swapanjeet?

    verilog pli book Any suggestions on which is better - sutherland vs swapanjeet ? Thanks
  7. S

    Which processor is the best for small SoC?

    For what kind of application?
  8. S

    PLI refernce material

    No, I was referring to verilog PLI. I did look around and looks like it needs to be purchased from IEEE.
  9. S

    VERILOG PLI READING MATERIAL

    Hi pravi, Can you pass me the link to your notes? Thanks
  10. S

    PLI refernce material

    Can anyone point me to PLI refernce manual? Thanks
  11. S

    RISC Processor verification suite or application programs

    Re: RISC Processor verification suite or application program If you are looking got MPEG softwares, take a look at mpeg.org
  12. S

    Where can I get the "HDL Chip Design" book by Smith?

    Re: HDL Chip Design book It would be great if you can compres the file and send it. Thanks
  13. S

    help needed in getting started in ASIC

    I have found that "hdl chip design" by Douglas J smith to be a good starting point for FSM. Also look at MIT course materials. I have the link somewhere, I will post it when I get a chance.
  14. S

    Where can I get the "HDL Chip Design" book by Smith?

    Re: HDL Chip Design book I could not access the website link to download. Can you please post the link or e-mail to viji_sandy at yahoo dot com Thanks
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