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Recent content by sai_shashi

  1. S

    Default values of wire and reg in Verilog

    Hi All, I know that the default values of wire and reg in verilog are z and x respectively. can someone tell me why it is so? Thanks shashi
  2. S

    Confusion regarding HI skew and LO skew gates.

    HI there, I am preparing for VLSI interviews. When i was studying on skewed gates i got this doubt that how downsizing the nMOS will favor the rising o/p transition and downsizing pMOS will favour falling o/p transition? I am really confused. Can someone please give me an intuitive...
  3. S

    understanding the memory specifications

    HI there, I was reading about different types of memories and I came across this question: How many words can a 16x8 memory store? Firstly, what is the meaning of 16x8 memory? and what is a word? Thank you.,
  4. S

    problem in sending and receiving data to a fixed point IP core.

    So i need to convert fixed to binary and send, is it?
  5. S

    problem in sending and receiving data to a fixed point IP core.

    Hi thanks for reply. I am going to use fixed point decimal. Here is how i have defined my fixed point data: typedef ap_fixed<22,10> data_t; data_t a=55.12; data_t b=21.32; data_t c=32.12; can you tell me how i can send it to IP core which only takes u32 data types?
  6. S

    problem in sending and receiving data to a fixed point IP core.

    HI there, I have a simple fixed-point adder written in HLS. I exported it as an IP core with Axi-lite interface. After completing the design in IP integrator i have written an SDK C++ app. But the functions that are generated for sending inputs show me that, i need to send u32 Data. But my...
  7. S

    using fixed point design in vivado SDK

    Thank you.. i went through the code. It is really helpful. What i am still not clear is that how do i send Fixed point data typed to IP core through SDK and display the FP data. I have added fixed point library from HLS to SDK but the result gives me only random values. can you please help me...
  8. S

    Problem in connecting the IP cores to DMA with microblaxe

    HI , Thanks for reply.. I dont use Tcl scipt, I use GUI directly. Here is my complete design in IP Integrator.. Can you please tell me where i am going wrong?
  9. S

    Problem in connecting the IP cores to DMA with microblaxe

    Hi there, Thanks for reply.. M_AXIS_MM2S and OUTPUT_STREAM have 200Hz and 100Hz respectively. But i am not able to change the frequency for M_AXIS_MM2S because it is fixed. what can i do? How do i change the frequencies between blocks?
  10. S

    Problem in connecting the IP cores to DMA with microblaxe

    HI there, I have a HLS generated IP core , which I want to connect to Axi- DMA with MicroBlaze processor. I get the following error. Can someone guide me here?
  11. S

    using fixed point design in vivado SDK

    Hello there, I need to deal with fixed point data types in Vivado SDK to send data to a fixed poing IP core. Does anyone has any idea.? Thank you
  12. S

    Need help in deciding the appropriate interface in Vivado HLS

    Hi there, I am developing a design in Vivado HLS which is compiling and giving the proper results. Now i need to generate the interfaces so that i can program it on the FPGA board. I have assigned the following interfaces to the core function: Function: void accel_core (data_in...
  13. S

    Unable to run C/RTL cosimulation in Vivado HLS

    Hi there, I have the matrix multiplication example code from xilinx which i am trying to implement on the FPGA. I defined the interfaces and performed c-simulation and synthesis. But to proceed, the C/RTL cosimulation field is inactive. Ho do i resolve this? what is the possible cause? Thanks...
  14. S

    using trigonometric functions in fixed point design in vivado HLS

    Hi there, The code i am using is : temp=imgons[i][j][k]* (data_t)sin(90); where i am multiplying a matrix of ones by a constant value, sine(90)=1 but in the output i get the following values: why is it so?
  15. S

    using trigonometric functions in fixed point design in vivado HLS

    i have changed into: temp=imgons[i][j][k]* (hls::data_t) sin(((float)(50))); It gives me the following error: Compiling ../../../core.cpp in debug mode In file included from C:/Xilinx/Vivado_HLS/2016.2/include/floating_point_v7_0_bitacc_cmodel.h:143:0, from...
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