Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by saha.123

  1. S

    Shielding of voltage lines with different value for same distance

    Hi, These lines will be a VREF type voltage dc signal generated at one place routed over some distance.How it will be affected in the circuit.?
  2. S

    Shielding of voltage lines with different value for same distance

    Hi, Consider the two voltage lines of 1V & 3V drawn parallel in layout for same distance.In this case, which one has the highest priority to shield? Thanks in advance.
  3. S

    CDM resistance calculation

    Hi What is the range of resistance will be kept for Rcdm resistor.HOw its calculated from CDM voltage like 200V?? Thanks in advance.
  4. S

    Coupling capacitance between clock signal and voltage signal.

    Hi, One voltage signal running in parallel with clock signal.Here,how the switching clock signal affects the voltage signal in capacitive coupling mode...??
  5. S

    N-well antenna effect

    Hi.... Could anyone explain about n-well antenna...How it is different from metal antenna??? Thanks in advance.
  6. S

    STI from all four sides

    Hi For any gate, Will STI effect come from only left& right side of the corresponding gate or it'll come from both top & bottom sides too??Could anyone explain it in detail Thanks in advance
  7. S

    Core layout separation from IO pads

    Hi Erikl, Could you explain it detail? If have any docs,please share Thanks
  8. S

    Core layout separation from IO pads

    Hi.... Why core layout is kept away(in few cases 20um) from IO pads? Thanks
  9. S

    Metal Spacing estimation

    Hi, What defines the spacing between the metals??The minimum spacing for same metal get increased by increasing the width.On what basis this things defined in PDK?? Thanks in advance
  10. S

    Diode based ESD protection

    Hi.. How does the diode protect internal circuit from ESD?Is it same type criteria for both input & output side??How diode protection differs from ggNMOS protection?? Thanks
  11. S

    Layout design for ESD

    Hi...... Can anyone explain about basics of ESD & ESD protection methodologies in analog layout IC design.please share if have any documents. Thanks in advance.
  12. S

    BJT layout matching in bandgap ciruits

    In band gap circuits, in layout if we have bjt 1:8 or 2:16 ratio the matching is done in such a way by keeping one bjt in centre and the remaining 8 surrounds the centre one(3X3) format.Can any explain the reason behind these matching concept?? thanks in advance
  13. S

    Current flow in device matching

    Hi..... In current mirror matching.... How the direction of current flow is important in layout matching either in interdigitizaton or common centroid?? How is it related with chirality of device placement??? Thanks in advance
  14. S

    resistor matching in layout

    Hi all....... Why interdigitization is preferred over common-centroid in resistor matching layout???Is it routing complexity of latter one???? Any other reasons??? Thanks in advance
  15. S

    spacing beteen different n-well

    Hi dick_freebird.... It'll be helpful to us if u explain detail...... Thanks
See more

Part and Inventory Search

Back
Top