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the bsim cmg models before 2019 all have a benchmarking test folder and in those test files we use bsim verilog file with two modelcard.pmos modelcard.nmos files. i can't find such a thing in bsim-cmg 2019.any idea why? are those model files no longer needed in 2019 version.?
hi. i'm simulating a dram in hspice and there is the read bit line that needs to be precharged before wordline read affects. the problem is i don't know how to precharge bitline .i saw some people use .ic for precharging sram bitlines and i tried that on dram but the voltage comes and goes after...
hi i am analysing just one transistor behaviour in hspice and cscope and there is a problem. with .plot vth(m1) there comes a lvth(m1) wave in cscope and it is measured in lv instead of volts. is it the same as volt? also how can i have a x axis with different gate lengths sweeps in cscope?
Hi.i want to make a circuit with finfet transistor library that i downloaded from ptm site. but it is a zip file with five .pm format files.
How shoud i use it in hspice?I'm kinda new to hspice and ita confusing cuz it's not the usual .lib format😑
hi here i was designing a flip flop circuit in hspice and wondered why is there a pmos source in m21 connected to nmos drain in m22?does it function as inverter?
hi. i created a 3 stage ring oscillator using 180 nm technology.my problem is when i try to compute the tphl from formula it doesn't match with what i got from analyses.
***ring oscillator***
.param Supply=2.5
.temp 70
.param WP=780nm fal=1 ris=1
.GLOBAL vdd
Vdd vdd 0 DC='Supply'
.ic...
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