Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello
I have designed an LNA. Is there any one who can urgently help to connect this lna to chip frame/ bondpad frame?
I badly need help. Please reply.
Regards,
Sana Arshad
Hello I am getting the following error after I include bondpad in my design. Can some body help how to remove the error?
Simulating `input.scs' on CadenceLatest at 7:01:53 AM, Fri May 15, 2015 (process id: 19524).
Current working directory...
Hello all,
I am designing an RF amplifier and in my design if I use a capacitor of 55fF between two stages, my S21 becomes smooth and wide as I need. The question is...is it ok to use such a small capacitor in RF design because it will be having a very high impedance and may be an open circuit...
Thanks a lot for your reply. Yes its home work :)
You initially wrote that I have to calculate for a periphery (width+2x Length) ...Please explain this
Now you have corrected for (2 * L).........Please explain this
Can you give me some reference. Regards
Hello...... can some body help me to find the answer of the question below? Regards
For the BSIM excerpt shown calculate the drain and gate capacitance for a 10um wide transistor in 0.35um CMOS technology.
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1...
Thank you for the reply. One another question is if S21 is a power gain and I get it from s parameter simulation of LNA. Then how can I find the voltage gain from this power gain in dB?
I have seen papers that when they have small power gains they report voltage gain so I need to know.
thanks...
Hello
I need an urgent answer. I am designing LNA and I am checking s parameters, dc parameters, ip3, p1db etc to check its performance. Now the question is I am also doing transient analysis and checking the waveforms at various nodes of the LNA.
If for any DC baising, I see that waveforms...
hello I intend to use PTM models of 32nm for LNA design. I have access to IBM 130nm techfiles only. Please correct me if I am wrong "I understand that for designing LNA, I must have inductors and capacitors of the same 32nm technology" and I cannot use the 130nm inductors or caps with the 32nm...
Thanks for your reply erikl. I have actually made a new library for PTM models and have copied two transistors (NMOS and PMOS) from analog lirary into it. Now I dont understand how to make the downloaded (.pm) file, the property of these transistors. I hope you can help in this regard.
Hello
I am just starting with PTM and want to use them in Spectre. I want to use 16nm PTM LP Model. Is there any one who can help step by step . I dont understand how can I take model details from PTM website to Spectre? Please reply in detail.
Thanks
Hello everyone,
I need some help for QRC extraction in cadence. I was running QRC normally for RC extraction only (using assura qrc) but when I tried to attempt to do rlc extraction i made some net selection. Although i did not succeed in performing rlc extraction but now if i do RC extraction...
Hi,
I am designing an LNA and at the output I have placed a source follower based buffer. This buffer is giving a constant S22 of -15dB from 660MHz onwards. However if I am checking the transient analysis of the buffer, I find that its vgs = 382mV and gm = 3.9mS, vds = 650mV, id = 200uA...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
