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Dear all,
I have designed a chip containing different blocks. Each block is DRC, LVS clean and parasitics have been extracted. At top level when I connect every blocks to each other, Calibre DRC and LVS is clean. The LVS shows exact match between schematic and layout. But When I do PEX to...
Dear Friends,
I am going to simulate the kickback noise of a dynamic comparator. Can any of you help me what is the testbench of measuring kickback noise? Shall I use resistive ladder (similar to Flash ADCs) to see the effect of kickback ? are the value of resistances important in kickback...
Dear Friends,
Recently I am going to perform a Transient noise analysis of a dynamic comparator. I have some questions: 1. How to set the parameters such as: noisefmax, noisefmin , noise scale , etc.
2. In output results how to draw the power density of noise at the output versus time? Now I...
Dear Friends
I wonder if you have good tutorial and examples of how to layout a simple circuit such as an inverter, and post simulate it. I also need to learn how to do the monte carlo analysis.
Regards,
Dear Friends
I would like to know if any of you has a simple help, tutorial and example of (for example: an inverter) how to layout and post simulate a circuit in Cadence 6.1. I do appreciate it.
Regards,
Samaneh
Dear friends,
As far as I am new in using cadence, I will be grateful if any of you would kindly give me any good tutorial or an example of how to run monte carlo analysis to measure comparator offset due to the mismatch of input transistors? or draw statistical diagrams. Unfortunately the...
Dear all
Recently, I have started working on calibration methods, particularly for SAR ADCs, but unfortunately from google and IEEE Search I couldn't find any comprehensive reference, I will be grateful if you would kindly introduce any good book, thesis or papers for introducing calibration...
Dear Friends,
Recently, I studied about Folding & Interpolating ADCs. I didn't undrestand how they actually quantize the analog signal? can anybody give me a clear guidance about how it works, any example or good paper that would explain the exact operation of it? I do appreciate you...
Dear Friends,
I'm going to simulate a SC integrator for biomedical applications, the input frequency is 4k and the clock of modulator is 1Meg . I would like to know how much GBW should have the OTA used in this Integrator and also I wonder if one can help me about the output waveforms , what...
Re: Adaptive Biasing
Thanx, about the paper you had leave me the address, the file had been removed, would you plz if you access IEEE, leave that paper for me? thanx
Dear friends,
does anybody know anything about adaptive bias circuitry used in OTA for improving Slew rate ? If so, wouldyou plz leave me great books or papers or introduce them?? Thank you.
Re: please,reply quickly can I design high speed op-amp on o
Dear Friend,
Orcad is not a good simulator esp in high frequencies, I strongly recommend you to use Hspice or cadense instead and you know in orcad the limitation of using about 100 I think transistors would limit you to design...
Dear Friend
You should first design a single stage and make sure that all the circuits are operating as well as you wish, then you cascade the stages to find the 12bit ADC , in order to undrestand the operation of the pipeline ADC I strongly recommend you to simulate it once with simulink...
Re: Current mirror OTA
Thanks,
Here is the name of the paper I told you about:
[1]. A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18- m CMOS
Good Luck
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