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Hello,
Im my design .. my launch flop's clock is 1.4ns and my capture flop clock is 10ns. The data is getting latched by capture flop in 4ps resulting in large negative slack and setup violation.
what would be the approach to solve this kind of situation.
Thanks,
S S Rayudu
Re: Multi cycle paths
Hello,
what are the practical problems occur by assigning multi-cycle path's to overcome setup violations. Any reply highly appreciated.
Thanks,
Rayudu
in my test bench im supposed not to give any test vectors for my 2 bit multiplier but test should be done for all 4 possible combinations by using for loops
can some one help me with this
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