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Re: About DNL problem
both ways are ok to quntify DNL. Only diffrence is that in first plot you can quantify only discreet levels. where as in second you can quntify the fractional DNL also. Now choice is yours i prefer second one.
Hey man your spec looks bit unrealistic.Huge input bandwidth. high osr. what process are you designing your ADC. from 3.3 volt kind of voltage its looks like .18u for this technology your spec looks like out of range.
noise in folded cascode
HI guys,
I was just wondering about the noise of the folded cascode amp.And i have following query(question).
1)Why the noise of bottom transistor in cascode is nondominant contributor towards the overall noise.
2) How to go about reducing the oveall noise of amp.
3)...
Hi,
rule of thumb says that the cmfb bandwidth should be greater then the bandwidth of the loop. Resone:- to compensate for common mode errors, like power supply noise, input common mode noise of previous circuit.
Re: vco bias circuit noise
Sorry, I've not worked much with bipolar. Why do you say, bipolar as tail is better? Is it only because, it has no flicker noise?
The only thing I can think of right now is to look at absolute values of other major contributors before and after changing the tail...
Re: vco bias circuit noise
The bias circuit can be a major contributor of noise in an VCO (especially in an LC VCO).
One way to reduce the noise is to increase the length of the bias transistors. This reduces flicker noise from these transistors
Reducing the mirror ratios by pumping more...
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