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I was trying to work out a similar situation for a verilog model of a flip-flip simulation in Cadence AMS. The FF outputs were not starting as 'x' until a clock edge or reset as I expected. With a gate level model of the FF using nands the outputs would start as 'x'. Eventually I suspected there...
If you are using a dual well process, then where there isn't Nwell (or Native) you will have Pwell implant.
Near the edges of Pwell you will get wpe effects.
OK thanks. In ESD Symposium 2002 paper "Optimization of Input Protection Diode for High Speed Applications" they found that n+/psub diodes were indistinguishable
from n+/Pwell diodes at high injection but they did highlightlight other issues.
Typically ESD diodes to ground will be n+ in Pwell, but in a process with native option n+ in psub without the Pwell implant is an alternative.
This can have lower junction capacitance so would seem useful for a lower capacitance ESD diode.
Are there any disadvantages for these diode types for...
DECIMM ESD simulation tool
Anyone tried this simulation software?
**broken link removed**
Thanks,
R
(No connection with angstromda)
[edit] Just corrected name in title.
I'll take the silence as a no...
Anyone seen any information about how MOS mismatch changes vs temperature?
For a circuit with trimming or calibration this can be important.
I found one source which claims matching improves at higher temperature but I would be interested to know if this has been found elsewhere.
**broken...
Yes sometimes pmos devices are used. They will need a larger area than nmos for the same ESD current. They are less prone to snapback breakdown which I assume is why they are sometimes preferred.
If you are making a large RC time constant with gate capacitance as the C don't forget that sub 0.18um generation thin oxides can have significant leakage so there will be IR drop across a large R. Got burnt by this when a foundry default model didn't include gate leakage.
The _mac & _mis are for mismatch modelling. The mismatch in the MOS devices will normally be more significant than bipolar mismatch in a cmos bandgap unless you use auto zero techniques..
Isn't it the other way round - for a current mirror where you are trying to match current the overdrive should be larger eg 300mV. The other constraint is the voltage headroom for the mirror devices, the larger the overdrive the more volts drain-source you need to keep the devices saturated...
mismatch with backbias?
Anyone got any information on the effect of backbias on mismatch? I have a circuit which is varying more than expected. The foundry model doesn't take the effect of backbias on the mismatch, which could be part of the problem. I found a few papers which showed mismatch...
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