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Recent content by RP

  1. R

    Pre-Layout Verification

    Hi, how did you define pre-layout verification ? As far as i am concerned, we use simulation-based and/or formal verification to verify RTL code, and use equivalent checking tool to check layout against RTL, and use STA for timing-verification. RP,
  2. R

    [Need help]Verilog simulation models problem

    Hi, I did not quite understand your question. But if you are trying to configure the verilog module, use compiler primitives like "#define cve". RP,
  3. R

    WHICH ONE IS THE BEST EDA TOOLS FOR ASIC DESIGN FLOW?

    Hi there, when we are talking about design flow, we usually mean the whole process from design spec, RTL coding, simulation/verification, P&R, etc. There are a lot of EDA tools involved in the flow. For our company, we use Cadence and Mentor tools for front-end flow, and Megma for back-end...

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