Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have tried to add 'fnl' in .simrc file. And the output netlist's pin is set by cadence itself. For example: the pin I set in the schematic is VDD, but in the netlist it becomes n3. And there is a sentence also: EQUA n3=/VDD. Why?
I also tried to get flat netlist by setting the simulator of...
How much loading is added when we simulate the standard cell and I/O? And how to decide the W and L of mosfets? What parameters do we care? fall time? rise time? setup time? hold time?
with the circuit and the input voltage you gave, I get the output voltage Vout2 is to be 1.4V by theoretic calculation. Have you checked the output range, gain and BW of the op?
The Vout = 2Vin-Vref mentioned by many books is not the Vin in this diagram. You can comprehend it as this, the first stage: Vout1=Vin±Vref, second: Vout2=2Vout1±Vref, ..., and Vout1, Vout2, ..., are not the Vout in your diagram. It's the voltage at the left side of the ×2 block.
You don't need to know the value of Vcontrol. The value of Vcont is a variable, and it varies until the loop is stable. You can just simulate the PFD, CP and LPF without VCO or dividers. What freq does not matter.
I think you have to consider the GBW, capacitor size and phase margin(with compensate resistor) together. Formula calculation can only provide a round value.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
