Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by rojyar_2020

  1. R

    who have LEDIT technology file ??

    Dear Dr. safari cadence is more useful for designing and layouting purposes. I strongly recommend it to you instead of Ledit. regards
  2. R

    What does Cadence PSUB stamp error mean?

    put a "m1-psub contact" near the VDD and connect it to GND node in ur layout.
  3. R

    who have LEDIT technology file ??

    thanku! it usful for me! I hope that this tech. files be helpful
  4. R

    cadence layout DRC errors

    I meet thease DRC errors in my Layout in cadence 1. off grid polygon in layer poly, NIMP or... 2.figure having no stamped connectionS. N+SD to Psub tap spacing must be <=10u it should be mentioned that thease errors occur even i draw only one transistor using its standard library...
  5. R

    Cadence DRC Design Error

    I have this problem too :( It occur even i put only 1 transistor in LSW window!!
See more

Part and Inventory Search

Back
Top