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Recent content by Rohit Ranjan

  1. R

    Verilog for loop error.

    Thanks alexhugo, Now I am getting an error that say 'iter' is an invalid type in Generate loop. Must be a genvar
  2. R

    Verilog for loop error.

    I am encountering this error. I think I just need someones second eye on it. Tool: Modelsim Error: near "+": syntax error, unexpected '+' Here is the section of code initial begin // Populate the memory. firstvalue = 10; for (iter=0;iter<=20;iter + 1) begin mem_array[iter]=...
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