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Error : Unable to map design without a tristate buffer or inverter. [MAP-1] [synthesize]
We are using genus 'Version: 21.10-p002_1', and the whole run went for a couple of hours before throwing this error. Could you please help with this, any idea what might be causing this issue?
Thanks a lot!
I want to get the timing analysis (or combinational delay) for one specific set of inputs. Is this possible using dynamic timing analysis?
And could you help me with how to perform this using PrimeTime?
Thanks!
Regards,
Rohan
Hi all,
I am looking to get the critical time of a circuit when specific set of inputs is given. Example, for a 4-bit multiplier, I want to check the critical time when multiplying 8'd4 and 8'd3, and when multiplying 8'd1 and 8'd2.
Is this possible with Primetime? Could someone guide me how to...
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