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Re: assembly programming
Actually, assembly language differs a little from one to another processor. Semantics can be different. A set of commands may be (should be) different.
As for microcontrollers, their core is microprocessor. Roughly speaking microcontroller = microprocessor + I/O...
For what are you using these delays?
You describe your device operation by this? Then it will be not synthesisable RTL-model. And you can not get the real implementation of this model.
If you wanna get real device you should use counters for this purpose.
1. Synthesis determines whether you have critical path and what is it (start -> end)
2. With aid of Modelsim you can look through DataFlow to find specific information about this path.
You are wrong, gokulka .
RTL. RTL description of the device is a model (like mathematical model). RTL describes behaviour of the device. That's why RTL-model is also called "behavioural" model. But usually RTL doesn't deal with real implementation of the device. Moreover, not every RTL can be...
Ok, I think this question can be considered resolved.
Our clock gating design is ok, though it is kinda special :-)
Thanks a lot! I figured it out! :-D
Great forum!
Ok. After setup_macro execution I got SE = 0; EN = X. Do you propose to write in register controlling EN?
I think it's not usual... During setup_macro it's supposed to setup JTAG controller
---------- Post added at 00:37 ---------- Previous post was at 00:36 ----------
And EN is controlled by...
No!
Master Clock = 0 -> CLK(latch_posedge) = 1 -> latch_posedge is in HOLD state -> gclk_n = (ENt | SEt), where:
ENt - value of EN at the moment of transition of Master Clock from '1' to '0';
SEt - value of SE at the moment of transition of Master Clock from '1' to '0'.
'C1' check is perfomed...
Ok. I agree it's just different. Then let's move to another question :-)
I got violation C1 caught on the domain gclk_n:
Clock Rule: C1
Clock PIs off failed to force off clock input N of scan S I (G).
Default Severity: Error
That's true. When Master Clk = 0 then gclk_n = X. So, I should just...
So, this design is better?
P.S. We also use Internal Scan technique, so in fact the latch_posedge has the port SE (ENL = SE | EN). And TetraMAX didn't like the design with uncertain clock OFF (when Master Clock = 0) value of the registers in gclk_n domain (1'st variant of the design). That's...
Hi, guys.
We use clock gating in our project. Our IP SC library contains only one type of clock gating cell - latch_posedge.
The excerpt from the project is presented here.
As you can see there are 2 clock domains generated from the Master Clock. I have doubts about correctness of this design...
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