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Recent content by rogerqin

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    SNR issue of 2 order 1bit sigma delta dac

    sigma delta dac harmonics Dear all There is a strange problems when testing 2 order 1bit sigma delta dac: When applying -3dB signal, there are harmonic distortion in the base band. This is normal. But when applying -60dB signal, there are still large harmonic distortion, which leads to poor...
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    help-how much my PSRR of ldo should be in my application?

    Re: help-how much my PSRR of ldo should be in my application For digital circuits, PSRR is not important.
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    look for good current limit circuit for LDO

    pmos ldo current limit Hi, WindRay Thanks for your reply. I have used such a method to design current limit circuit. The most important issue is the stability of the negative feedback loop. The best condition is that when the current limit circuit begins to work, the main feedback loop should...
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    look for good current limit circuit for LDO

    current limit loop stability circuits Hi, all Is there any good current limit circuit for LDO? Thanks for your help.
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    The size of pmos pass transistor in LDO regulator

    ldo with pmos pass gate I have simulate the transient loading variation, it seems no problem. I have not simulate the output noise, but only power supply rejection, which is decreased about 10dB than the condition that the pmos pass transistor operating in saturation region. If I can accept...
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    The size of pmos pass transistor in LDO regulator

    pmos pass transistor Hi, all I am designing a LDO regulator, the minimal power supply voltage is 4.75V, and the output voltage is 4.5V, the maximum output current is 20mA. In order to assure the pmos pass transistor operating in saturation, I have to set a large W/L, but i can not provide this...
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    Help: simulate CMRR of opamp

    Please help me to check it, thanks a lot.
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    Help: simulate CMRR of opamp

    A method of simulating CMRR of opamp directly is provided in Allen's book. The circuit configuration is as figure. The equations are: vout = (vp-vn)*Av+0.5*(vp+vn)*Ac vp = vcm vn = vout+vcm so we have, (1+Av-0.5*Ac)*vout = vcm*Ac. and vout/vcm = Ac/Av = 1/CMRR The spice netlist is listed as...
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    The influence of self bias to the gain of opamp

    Yes, this circuit has a positive feedback. My question is why this loop is stable and the gain is boosted from 50dB to nearly 90dB. How can I analyze this circuit? Thanks.
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    The influence of self bias to the gain of opamp

    Hi, hr_rezaee. NBIAS is the bias voltage of tail current. When I applied a constant voltage to NBIAS, the gain of opamp is nearly 50dB, but when self biasing as the figure above, the gain boosted to 90dB. The meaning of 'failed' is that I can not explain it with small signal model analysis...
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    Help me design a two stage op amp in Cadence

    Re: Ugent Need help As the supply voltage is 1.8V, I think the folded-cascode topology is more suitable for you.
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    Effect of input CM voltage on Differential Pair

    Consider the simple condition, that Av=gm*rds, gm=2Id/Vov, ro=1/(lambda*Id), so Av=2/(lambda*Vov). From this, we can see that the gain is determined not by Id, but Vov. Vov changed with W/L.
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    The influence of self bias to the gain of opamp

    Hi,all. Thanks for your help. This opamp is used in bandgap. I simulated a simpler circuit as the figure below. The same phenomenon occured. I tried to analyze it using small signal model, but failed. Please help me to check it, thanks a lot!
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    The influence of self bias to the gain of opamp

    When simulating opamp, I found that when applying a constant voltage to NBIAS, the gain of the opamp is nearly 50dB, but when self biasing the gain of the opamp boosted to nearly 90db. Who can explain this problem detailed for me, thanks!
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    Help:A strange problem when I using cadence ic5.0.33

    When I select an option in a list box,the option has been highlighted,but the option is not really selected,e.g I can not select any option.Has anyone encountered such a problem?Please help me,thanks a lot.

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