Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi ,all
I want to insert Jtag into my design,using Synopsys's design Compile.
This is my first design ,so ,there are some problems.
A: How to write the constraint script when synthesis the TOP-design including BSD and core_logic.
B: How to verify the design ,and which tools are...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
