Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello all,
I am trying to find a way to interface a DDR style memory (bi-directional, >500MHz/1Gtps) to an Intel Stratix 10 FPGA. The IO voltage of the FPGA can only go down to 1.2V (using the SSTL12 IO standard) and the VDDQ of the memory is 0.6V.
I have been doing a bunch of searching and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
