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Given the fact that derating is mentioned whereever you find reference to k-factors it is quite obvious to get confused but there is quite a lot of difference between k-factors and derating factors used for AOCVM.
If you open your.lib (or LIBERTY) :grin: then you will find something called...
SDF is a delay format , it could be written out of DC, IC compiler and PT all 3. The source of the delay differs .. From DC / ICC it could be Wire load models or TLU+ files. This SDF can be used for forward annotation / back annotation.
However, it is preferred to use SPEF in PT because we also...
No Tcons just means timing constraints ... ususally in tcl format ... mostly used by cadence tools like RTL compiler and EDI.
DEF or Milkyway is used to pass Floorplan/Placement info
Yes sir, they mean the same. Parasitics referes to resisitance and capacitance (RC)
Cheers
ro9ty
DEF/MW depends on your PnR tool. If Synopsys then preferably MW, if cadence then DEF.
Yes, it contains parasitic delays. As long as your routing is not done the tool will estimate interconnect delays and that is more accurate with TLU+ than with WLMs
Tcons is constraint files like SDC...
IO library comprises of IO cells- which have some additional circuitry like output enable, ESD protection etc..
It has additional components like : IO_Voltage which is the voltage that runs in the rails and is usually higher than the core voltage. The cells have the following :-
rail connection...
Yes, usually we do ignore min_cap violations but that is because we don't get it mostly. 9/10 chances it happens due to bad library characterization, if the library min_cap is very low then you are likely to see a lot of them.
Why it is bad is because you might have to add lots of...
You must have read in sdf file. If you do add repeater after reading SDF and not SPEF it will now not be able to compute new the new delay values because it does not have a table.
Hence, you see it unconstrained.
Please correct me if you are not using SDFs.
Thanks,
ro9ty
i/P files -> RTL files/ netlist, floorplan details (any physical info), you can take TLU+ you can use SPEF, of course libraries, - thats basically what you need.
SDC/Tcons for optimization
O/P - A lot of things - netlist, sdc, dofile for lec, svf files, etc..
No RCA.. there is an ambiguity in what i have written here. Yhanks for pointing out.
No, only NAND/XOR gate cannot do the test because it cannot retain and pass test vectors. We had an internal bunch of registers known as non-test registers. What i mean bu NAND/XOR is that suppose there are 5...
I don't know exactly what you are referring to there are two things.
Z-route is usually one way of routing also called double bend routing where a global route is made using double bends.
Another thing is a feature that was introduced in some PnR tools called Z-router which use an advanced...
DC topo has lots of additional features which gets modified with every subsequent release which are not available in DC and hence there is quite a lot of difference. However, yes the endpoint is same- DC topo is more accurate but what makes it so makes the topo features different.
Ro9ty
Sharath is correct but there are many different ways in which a DC-topo is used.
The work of DC topo is to allow the tool to optimize better based on other inputs like physical constraints, physical only cells etc... that we usually do not provide to DC in normal mode.
For physical constraints...
Your question has been amply clear right from the beginning, nothing extra-ordinary in it and i have given you all the facets of constraining the input paths in the simplest possible way.
@Layowblue has brilliantly summarized the whole thing. Hope it helps !!
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