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Is it possible in Verilog/System Verilog to inetrconnect with a single net different signals of (different vector widths) of different instantiations?
when I tried this code in ModelSim I dont get any compilation error. But with VCS I am getting compilations error. I want to know if it is...
I have a module definition (ckuclkucsisliced) as follows. I am using this (ckuclkucsisliced) multiple times in another module (ckucsislicepgd) as follows:
module ckucsislicepgd (
input pguclks10,
output [57:1] ckucsigd
);
wire [4:1] pguclks14;
wire [ 19:1] pguclks17...
I am trying to compile this verilog code. I am getting this error message. I am not able to understnd this error message.
Error Message:
# ** Error: /nfs/iind/disks/egl_fe_0001/people/mrangapu/spine/clock/x.v(21): near "endmodule": syntax error, unexpected "endmodule", expecting ')'. 21st line...
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