Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by rk_learn

  1. R

    How to write parasitic file using Design Compiler for a hierarchical design

    Looks like your link_library setting is wrong. Use set link_library "*"
  2. R

    How to write timing constraints

    Hi, I would like to understand the procedure involved in writing timing constraints for a full chip. And how to convert the full chip constraints to block level constraints. Currently I am following this procedure: 1) Read the netlist 2) Do check_timing and find out all the flops which dont...
See more

Part and Inventory Search

Back
Top