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I only can find some info to avoid metal 1 above matched transistors, since i can have an impact on Vt. This makes perfect sense to me. There is no info I can find for other metal layers or vias, or just vias in particular.
But if there is no M1 there is also no via1. And if you have a via in a...
Is there any problem in placing a via above a MOS gates? I don't mean the contact between poly and metal 1, but a via between 2 metals.
Can this have impact on the matching in an array, even if the via is the same above every MOS in the array?
In I3T50 technology with 5 metals, the top metal is thicker as the internal metals. This results in a lower resistance, 55mOhm/sq for internal and 33mOhm/sq for the top.
The maximal current in those metals however is the same, 1,1mA/um. I should expect also a difference here, what can be the...
Only if you don't overlap the sources. If you place 2x2 transitors with 2 fingers in an XYYX configuration (perfect common centroid), the source can be overlapped if connectivity is the same. LOD effects Sa and Sb will not be the same for transistor X or Y. Y is more to the center, so less...
Is it correct to assume that STI stress is an non-linear effect?
If so, overlapping sources in a matched array will cause a mismatch. Even if the layout is perfect common centroid.
Is it correct to assume that problems with STI stress start to arise from nodes below 130nm?
I am looking for a good methodology for sharing of source terminals in matched devices.
Has the sharing of sources any impact in a current mirror? Is there any mismatch introduced by STI stress or LOD effects?
Would you say it is a good idea to never share the source between matched devices in...
Is there any rule of thumb for the dummy size in a highly matched MOS array?
From what size you start reducing the dummy size, or is it better to always full size dummies?
On my 180nm process, the checking window for density is 1x1 mm. If you make a smaller asic (4mm sqr), it is possible to make this very un-uniform, since the asic is only 4 times the window.
Are extra precautions needed? (like forcing a smaller density window)
Imagine I have a Pmos, witch runs a high current. I want to know if there is any leakage between the bulk of my Pmos (the Nwell) and the p-subsrate?
All I know now is that a high energy holes in the channel can break a bond in the N-well, and the resulting pair is evacuated by the bulk contact...
The N+ first, it sits in the same well and doubles as bulk contact. You always need the bulk, so why not make a ring of it. Then the P+ to pick up substrate noise. You can then add another N+/NW ring around that. This will force the passing noise deeper into the substrate (more resistive)...
How do you connect the substrate?
Every building block I use has a separate net for Vdd, Vss and Vsub. The Vsub net connects to the Vss pad using a star connection. Since I assume that the substrate doesn't run any current, this is a small connection.
Is this correct, and if not, what kind...
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