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Hi, everyone, i'm designing a 1:8 demultiplexer using CMOS 65nm technology. It works properly @ 2.5GHz, but fails @ 5GHz or even higher frequency. Can anyone tell me how to improve the speed of demultiplexer? Thanks in advance.
The schematic is used as attached. The transistor width i used is...
hi, mishu_b, tks for reply.
I run 2 DC simulations, sweep one input voltage from 0 to Vdd and back, but the results are the same. i can not see the hysteresis window... is there anything i did wrongly? tks again
hey, everyone, i'm designing a hysteresis comparator (to detect small signal pulse and convert it back to digital data). The schematic is from Allen's notes. But i'm not sure how to look at the result, how to obtain the offset voltage and hysteresis window... All i know is to perform a DC...
I'm designning a 60GHz push-push VCO in ads. When set the noise ports as differential nodes (@30GHz) in HB noise controller, correct phase noise (pnmx) is given, around -70dBc@1MHz offset. But when set the noise port as single-ended (@60GHz), i got positive pnmx value... I've changed the osc...
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