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Yeah, thats right. I changed it to present_state <= 16;
but now when i simulate the code the signal s16 doesnt seem to do anything? How do i fix this?
Thanks alot for all the help by the way!
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Not sure if you can see in the picture but all it seems to do when s16 is 0 is...
Hey there!
Im new to VHDL and im getting "unresolved signal is multiply driven" at --> <-- this line in the code. What does it stand for and how shall i recode to resolve this issue?
Im just coding a 5 bit counter that can count up and down that doesnt pass 0 when its counting down and doesnt...
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