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you can create a top module where you can instantiate all the other modules. like as follows ..
module TopModule(outputs & inputs here of the whole box containing the small boxes);
output ...
input .....
wire *instantiate some wires here to connect the modules among themselves*
//Now...
from what i can gather u need to design a state machine. You should read up on Mealy or Moore state machines. The code that you've written can work in principle. Just use a MAX value at 8 which can bring your counter back to '0'.
sounds quite perfect to me since it has a side of controls in it aswell but it sounds intimidating too ...
could you guide me to some online material i could look into regarding this.
trying to avoid such applications because its an individual thesis and working of hardware will make it very difficult alone. Any ideas on image processing or filter implementation which isnt very common but not very complex either ?
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Major is in Automatic Control Systems...
AoA Guys
I need help in choosing a proposal for a project/thesis using FPGA kit. I have access to a Xilinx Spartan 3e in my department's laboratory and could also get it issued if needed.
There are a few posts on this topic before, i know but I couldnt find a suitable answer for myself. The...
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