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Recent content by research_vlsi

  1. R

    digital waveforms in microsoft visio

    Use Timing Designer tool for drawing waveforms..
  2. R

    TCL script for bdf to RTL

    Hi all, i am working in quartus 9.1, some design files are in bdf. direct method is available with quartus. But I need TCL script to convert my bdf files to VHDL. thanks
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    Nexys2, ditributed RAM and block RAM

    You are Coding a RAM for some purpose in your design. Depending upon the size of the RAM, synthesis tool will infer Block RAM or Distributed RAM. Most FPGA boards have dedicated Block RAMs. So if you code a large/big RAM synthesis tool will infer Block RAM. on other case if you code a small...
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    Verification methodology of motion estimation in H.264/AVC

    Re: Verification methodology of motion estimation in H.264/A well as u said u use JM reference C code, give your testing bit stream to C reference code, extract the results to a text file. same you do that for HDL. compare the two files. so that C generated result and HDL result will match if...
  5. R

    interview qstn on comb ckt to remove less time pulse

    Design a Buffer with 5 ns inertial delay.
  6. R

    Verification methodology of motion estimation in H.264/AVC

    Re: Verification methodology of motion estimation in H.264/A Hi Let me know which HDL u are using? whether u written full RTL code for ME?
  7. R

    Perl script examples through which we can automate modelsim simulation

    Re: perl script examples Thanks Pini_1 I saw those link. Can u get some basic perl script that related to EDA, not more complicated.
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    Perl script examples through which we can automate modelsim simulation

    Dear all Am learning perl. I need some perl script examples through which we can automate modelsim simulation. using active perl am learning. looking for the reply's... thanks...
  9. R

    design compiler student workshop

    Re: clock skew This book will help u Digital integrated circuits - rabaey Chapter 10.
  10. R

    PLZ ... Help me !!! increment the address of SRAM

    1. assignments inside always block should be declared as "reg" 2. inout variables should be declared with continuous assignment statements (assign) try this output reg [17:0] Address; // RAM Signals // include reg inout [7:0] Data_Bus; output nRD, nWR; output nUB, nLB; output nCE; input WE...
  11. R

    how to simulate my coregen in modelsim?

    Re: reg xilinx coregen Hi guys Thanks for your answers.. Finally i got a solution.. my core is simulating in modelsim. I did the following steps 1. In ISE, select the device in the sources window 2. find the the "Compile HDL Simulation libraries", right click and select "Properties" 3. Set...
  12. R

    how to simulate my coregen in modelsim?

    Re: reg xilinx coregen thanks a lot guys.. I executed compxlib utility.. Its installed. How to map those library to my modelsim.. am getting error " Instantiation of 'fifo' failed. The design unit was not found."
  13. R

    how to simulate my coregen in modelsim?

    reg xilinx coregen Dear experts I have a doubt in coregen, how to simulate my coregen in modelsim. How to map the library of xilinx with modelsim? Thanks in advance..
  14. R

    Questions about using and learning Perl script

    Re: perl help am upgrading on PERL. I need help regarding how to write a perl script to automate the operations in Modelsim. Like compiling, simulating, adding wave... am working on windows... whether its possible to invoke modelsim through a perl script? kindly help...!
  15. R

    What's the difference between '#5 a = b;' and 'a = #5 b;'?

    difference between 5a and 5b Simulate in Modelsim and check..!!!! # 5 a = b ; Its Inter assignment delay a= # 5 b ; Its Intra assignment delay Intra-assignment delays block assignment but not evaluation Inter-assignment delays block both evaluation and assignment For details refer any...
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