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Re: ldo
i am getting spikes magnitude in volts(>4v).i want spikes magnitude in milli volts.for this what parameters should be improved..................please give me reply as soon as possible.............
i am designing capacitorless ldo ,i/p is 2v and o/p is 1.8v......getting good stability.But for transient response when i am applying 0 to 50m current step,o/p voltage is getting reduced to almost zero when current is changing from 50m to 0m.why this much spikevoltage is appering.please help me....
Re: ldo
For ldo i am getting good phase margin(80deg) and gain(76db).but iam not getting good transient response(getting spikes in volts)............what factors(i.e GBW,phase margin)should be improved to get spikes in millivolts
Re: ldo
thank u for the reply...for transient analysis i hav given current pulse from 0 to 50mA pulse width=50u and period=100u.for this excitation i plotted output voltage.from this graph how to measure settling time.i am doing this project on cadence tool. settling time means what for...
i am doing project on ldo.for this one i plotted load regulation and line regulation and also i did transient analysis.but i dont know how to calculate load regulation ,line regulation and settling time from the graph.....please help me...:cry:
Added after 6 minutes:
Re: what is error amplifier
depending upon requirement design error amplifier .if u want to improve the regulation charcteristics increase the gain of the amp by using 2 or 3 stage amplifier..but u have to make sure that system must be stable ...
ldo book
read ieee papers on optimum nested miller compensation for low voltage low power cmos amolifier design,a frequency compensation scheme for ldo regulators,analysis of ldr topologies for low voltage limitation
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