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Recent content by rd15

  1. R

    FPGA Verification - how to give input bits and get output

    Re: FPGA Verification! I think you didn't get me. I have already programmed FPGA using ISE Webpack software. Now I actually want to use this FPGA for working. Thanks...
  2. R

    FPGA Verification - how to give input bits and get output

    FPGA Verification! Hello all, I am a first time FPGA user. I have programmed a Xilinx FPGA using VHDL and now want to use this FPGA for practical purposes. I do not know how to do that. How will we give input bits and how will we get output? Thanks...
  3. R

    How to see the encrypted image in VHDL?

    vhdl read bmp Hello, Thanks a lot for your response!! Can you please tell me how can I use that data in VHDL? I mean where do I use the file created by MATLAB. Do I have to use that in a testbench or some separate file? I have VHDL code for an algorithm, which actually processes the image...
  4. R

    How to see the encrypted image in VHDL?

    Hello all, I am working on an image encryption project. I have written VHDL code to encrypt a plain image to encrypted image according to an algorithm. But the problem is how I can see the actual encrypted image using VHDL. Can I directly feed a bmp image to VHDL code and after processing, take...
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