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Hi friends,
I have a simple testbech with these signals:
reg rst, clk;
wire line1, line2;
wire outp, overflw;
In the do file I wrote (I know I could have simply written that as: vcd add /tb/*):
vcd add /tb/rst
vcd add /tb/clk
vcd add /tb/line1
vcd add /tb/line2
vcd add /tb/outp
vcd add...
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