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Recent content by ravurig

  1. R

    How to view a sinewave in Modelsim?

    Check by expanding and zooming in window Atleast some signal should be visible If not check ur digita data in hex Is it a sine/cos data in hex format? Check the above two points first.
  2. R

    verilog rtl handling interrupt trig n interruprt clear simultaneously needed ?

    In rtl, poll for Interrupt status it. If set clear interrupt. If you are using "arm" easy testbench, modify C-code to add an ISR routine.
  3. R

    Timer0 and INT interrupt in PIC16F628A

    Check in htc.h file, looks like the defined memory location is not available in H/W
  4. R

    FPGA implementation of feature extraction module from images

    if it is simple algorithm and if possible send me your code, I will try to make verilog code.
  5. R

    NVIDIA Interview question? ASIC Verification

    nvidia asic golden reference model should be there
  6. R

    What will be the successor of 3G standard?

    what will be next after 3gs LTE(Long Term Evolution)
  7. R

    SystemVerilog using DPI

    using dpi Hi , I am using the above script for running co-simulation(C-code & SystemVerilog). But I am not able to get my waveform file. Lines written in testbench to dump wave. ----------------------- initial begin $recordfile("./wave/TD_TST.trn"); $recordvars; end...
  8. R

    Looking for an engineer to work from home on project basis

    Re: Work from home Is it Baseband processor using verilog or matlab??? may be more details will be better.
  9. R

    mobile communication project on matlab

    fpga project reports hi , hw did u model channel model. Is it Ricean or Raleigh ....... I didn't see any packet or frame detection. Nor a Equalizer ,nor a Synchornisation circuits like coarse synchronisation(or symbol boundary detection), coarse frequency offset detection, fine time and...
  10. R

    How can I convert .db to .v

    I think ur problem is not to convert .db to .v but to access ur .db library in a proper way check ur target library command
  11. R

    Question:what is Equalization?

    frequency domain equalizers are much simpler that time domain equalizers. In OFDM we implement equalizer after FFT,so here frequency domain equalizer is a simple Equalizer = FFT out/(CHannel Estimate) .
  12. R

    The function of radio frequency block in WLAN

    Re: WLAN first understand transmitter part from IEEE standard,then u can think of Receiver part.U can download stndards.
  13. R

    Verilog coding for smaller mux?

    I think u should check the relation between the case 4'b1000 with other cases ,if some relation exists then u can implement only 2:0 mux. Lets say 4'b1000: x = ~y; 4'b0000: x= y; In the above case u don't require to write explictly 4'b1000. use 2:0 mux and when [3] is 1 take output...
  14. R

    a question about viterbi decoder

    Hi , In compare and select u set (a<= b)? "0" : "1" and during traceback choose best state as state having minimum value. But at the start of traceback(while choosing best state),if two states are having same value,then something is wrong.
  15. R

    How is .lib converted to .db?

    Re: .lib read_lib ram.lib write_lib RAM_LIB -format db -o ram.db no need of library compiler

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