Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hai buddies... I am new to High speed radio frequency layouts. So , i want to know what are constraints that should be kept in mind while doing layout of RF circuits like (amplifiers and bias circuits). :grin:
:roll:In order to avoid antenna effect during process fabrication, we will aviod usage of long inter connects or poly directly to the gate of mos transistor, using jumpers, bridges, net area check diodes will be added.
Now i want to know apart from the above mentioned methods is there any...
If the layout dimensions exceed the specified dimensions, what are the possible approaches to reduce the dimensions of a block or at chip level??
This is one of the question asked me in an interview.
Any sort of help is greatly appreciated
thanks and regards
ravi
my mail id is...
Hi guys...... I am new to analog layout design. I want to prepare my resume.I want these modules on layout
1. SERDES.
2.PLL.
3.ADC.
4.Standard Cells
5.BGR.
Can anybody kindly Please send me the model resume on the above mentioned topics regarding layout.:-D
My email id ...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
