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Recent content by RaviT

  1. R

    How to connect two FPGA(Nexys-4 of Artix-7) as one Tx(output) and other Rx(input)

    actually the problem is i am not using the UART available to me at board....i m designing UART of my own as my project.... so while demonstration(presentation) i need to show communication between separate transmitter and receiver present at different FPGA boards
  2. R

    How to connect two FPGA(Nexys-4 of Artix-7) as one Tx(output) and other Rx(input)

    i am facing some problems while connecting two FPGA boards such as: 1) how to extract output from the USB port(instead of LED or display like usual) of the Tx FPGA board? 2) how to feed(provide) data input to Rx FPGA board module via USB cable(instead of slide button or dip switches like...
  3. R

    How to connect two FPGA(Nexys-4 of Artix-7) as one Tx(output) and other Rx(input)

    i am designing an UART (as my project) using verilog HDL, i need to put my transmitter and receiver modules on different FPGA(nexys-4 of Artix-7 series) boards and finally do the communication for the on board testing of my UART design, but i don't know how to connect two FPGA boards in such a...
  4. R

    [SOLVED] Can someone please tell me the meaning of this verilog code:

    parameter data2 = 4; reg [data2-1:0] data1; if(data1=={data2{1'b0}})

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