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Recent content by RAVINDRA SINGH

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    Hello, VHDL code for vector to integer conversion needs some light to be shed upon

    Thank u tickydicky, that was realy helpful. so FPGA's use mux for tri-state logic?
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    Hello, VHDL code for vector to integer conversion needs some light to be shed upon

    Trickydicky....thank u for ur suggestion.I must admit that I have written the codes in form of a language rather than an HDL code for hardware. This is because I haven't been taught VHDL in terms of hardware, that's what I am pissed about till date, i want to know about the HDL in terms of...
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    Hello, VHDL code for vector to integer conversion needs some light to be shed upon

    yes Barry, first of all , sorry for replying so late. yes i am trying to read from port b , update it and again write to it y taking b as an in-out port, well what i saw that only the last statement is executed i.e to say the loop creates all the iterations but only processes the last...
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    Hello, VHDL code for vector to integer conversion needs some light to be shed upon

    hello everyone, i have a question that popped up during the design of vector to integer code. Leaving asides the use of variables inside the process statement , if we use an inout signal and update it as in the following code, i thought it would work, however it's giving unexpected results...
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    fundamental period for DT seq x[n]=cos(pi* (n)^2 / 8 ) ?

    Re: fundamental period cos ( n^2) ====== hi buddy, i am a bit confused that why did we take n^2 = 4, why not n^2 =16, after all, it also gives an integer value and also the lowest value of N, also 32*pi/16 = 2* pi and added to 4* pi gives 6*pi, so that x(n+N) = x(n)
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    HELP WITH Vhdl assingement

    victor, can u please elaborate the problem, i am not quiet getting it, if i get the problem, maybe i can be of some help to u.
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    T-Spice error: "IVAssign1.sp" line 12 Missing MOSFET model definition for "CMOSN"

    Re: T-Spice error: "IVAssign1.sp" line 12 Missing MOSFET model definition for "CMOSN" Hi shiken, i too am very new to tanner t-spice tool. i too had the same problem. i downloaded the text files from mosis site for the model definitions and included them in the design and got the same error...
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    HELP regarding tanner v14.11 t-spice models

    hello to all knowledgeable people: i need help regarding the tanner t-spice models. i need the tanner t-spice model file(urgent) as well as the tanner libraries(though i have one). if any one has got tanner t-spice models, plz do mail me. :idea: ravi.ymca.vlsi at gmail dot com
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    [SOLVED] How we can test a capacitor....??

    Bro do you mean testing for whether the capacitor is operable or not:?:
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    [SOLVED] passive Vs active devices

    HI ACTIVE DEVICES ARE BASICALLY THOSE DEVICES WHICH CAN CREATE ADDITIONAL POWER AND BOOST THE POWER OF THE INPUT SIGNAL. ALTHOUGH THIS ADDITIONAL POWER IS SUPPLIED BY THE D.C SOURCE BUT THIS SOURCE IS NOT A SIGNAL(IT'S STATIC wrt TIME AND SIGNALS HAVE VARIATION WITH TIME) AND WE TALK IN TERMS...
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    [SOLVED] HELP....BASICS OF TRANSISTORS(Any help will be appreciated!)

    HI ANURAGMASH > ALTHOUGH THERE IS NO DIFFERENCE IN THE BASIC OPERATION OF TRANSISTORS IN ANY MODE i>e INTERNALLY IF YOU LEARN THE MICROELECTRONIC DETAILS. > NOW THE ONLY DIFFERENCE COMES THAT WHAT IS APPLIED AT THE INPUT AND WHAT IS THE OUTPUT. TREAT THE TRANSISTORS AS CURRENT CONTROLLED...
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    Problem while simulating the following code for memory

    HELLO EVERYONE THIS CODE OF MINE IS NOT WORKING PROPERLY ; CAN ANY1 SUGGEST WHAT IS THE PROBLEM WITH EXPLANATION AND ALSO THE REMEDY FOR IT. SUPPOSE WE INPUT(WRITE) 3 DIFFERENT DATA SAY x, y, z AT THREE DIFFERENT LOCATIONS: SAY LOCATION 0 ,1 ,2. NOW IF I WANT TO READ DATA AT LOCATION 0 ...
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    npn transistor action CE mode

    CE mode in transistors is widely used in amplifiers due to its best power amplification (voltage and current amplification included). npn transistor in CE mode: well here remember two important points while using transistor in active mode( it's actually general for all modes)...

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