Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
I've one basic doubt on difference b/w input referred noise voltage and input referred noise current.
For common gate stage input referred noise voltage is independent of gm of driver but noise voltage is dependent on it.
But both should produce same output referred noise voltage. Then...
hi everyone, I am trying to implement SRAM in cadence. So, I need to perform monte carlo anlaysis on SRAM and also I need to draw scatter plot of leakege current against process variation vth. I know how to set statistics block and running monte carlo but I donot know how to...
Thank you for your help. When I am trying to include both process and mismatches in my model file(.scs) I saw only mismatch block I couldn't find any process block and also I am confused with the statements in model files(in subckt section): varvt = .004 // 1 sigma Vt mismatch variation in...
Thank you very much for u r help. could u please tell me typical values of standard deviation of vth and tox for both process and mismatch. I am using 90nm node.
Hi everyone, Now I am working on process variation SRAM cell design. I need to draw histograms and scatter plot for vth. But i can't have them in the prameter list of histogram windows.I figured it out the problem partially we should give vth as process varible in static block of...
Hi everyone, I want to do project on process variation tolerant in SRAM in sub deca nano technologies. I am wondering if any one could tell me basic and good papers related to it. Please help me .
I'm getting histogram plot if I choose 'Process' in 'process variation' drop menu. Does this suffice my requirement(plotting variation in output CM voltage )
I've three options(1.Process 2.Mismatch 3.Process&Mismatch) available in 'process variation' drop menu, I know their meaning but I don't...
yes
yeah I've the same statements in my gpdk090_mos.scs.
Does this mean that there is no process variation?
I'm doing Monte-Carlo simulation on differential amplifier with CMFB. I want to know the variation in output common mode voltage due to PVT, is it sufficient to only opt for 'Process' in...
Hi all, I'm getting following error when I've chosen 'Process' in 'Analysis Variation'
mc1: Attempt to run Monte Carlo analysis with process variations, but no process variations were specified in statistics block. I don't get this error when I change it('Analysis Variation') to...
Thanks all,
I'm attaching 2 plots from transient analysis
in first plot 'out' is my final ADC output (output of mux,M1 ('/net0136') followed by buffer),2 inputs of mux are '/I21/net042' and '/I21/net037'(output from another Mux,M2) with 'fin' as control signal. '/net0136' is output of mux.
In...
Problem with difference in driving strengths of NMOS and PMOS transistors
Hi all,
I'm designing digital circuit(consisting of MUXes and full Adder) for my ADC. At the output of my digital block I'm getting postive glitches. It seems because of difference in mobiities of NMOS and PMOS...
Thanks Dgnani, problem has got solved. I've decreased, increasing its W/L, 'ON' resistance of top switch.Now I'm getting exactly what I needed. Now I get to know that resistance of Top switch should be in comparable to combined resistance of all bottom switches.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
