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Recent content by ravi_meghadri

  1. R

    How to easily write a table of values to a file (200 elements) in Verilog?

    hi friends! I have to write a table of values (constants) to a file. table contains 100 to 200 elements, each of 1-byte. Is there any simple way to do this. this operation need not be synthesizable.
  2. R

    I/O and power pads in floorplanning

    I am using synopsys flow
  3. R

    I/O and power pads in floorplanning

    Hello frnds! I have few doubts on libraries what is the extension for I/O and power pad library? what information does it contains? to do floorplanning, what all are the libraries we need? I posted the same doubt few days back, but looking for more elaboreted reply
  4. R

    Libraries for I/O and power pads

    Re: I/O and power pads what is an assignment file?
  5. R

    Libraries for I/O and power pads

    Hi friends! How to get I/O and power pads? I have standard cell libraries(.lib and .lef) with me. I heard that we need a seperate library for pads, Is that true? what would be the extension of pad library?
  6. R

    Do we need .itf file to add capacitance table to mw-library?

    Re: Doubt on Astro thank you mr.chyau.
  7. R

    Do we need .itf file to add capacitance table to mw-library?

    Doubt on Astro Hi! Do we need .itf file to add capacitance table to mw-library or can I proceed without .itf file? I heard that .itf should be supplied by vendor, but I don't have it. can anyone suggest me a way to work with Astro without .itf file or please share the file for 90nm, 6-metal...
  8. R

    How to initialise look-up tables?

    My design is having a memory unit and it has to act as look-up table. How to initialise it at the start up. It is of size 256 x 20 bits.
  9. R

    how to implement Look-Up table in verilog

    what are the various ways to initialise the look-up table?
  10. R

    Help me design a State machine for Traffic Control at a Four point Junction.

    state machine for this design u need to learn FSM design. Identify the states and follow FSM design steps
  11. R

    how to implement Look-Up table in verilog

    Hi! Anybody could help in writing a synthesizable verilog code for look-up table implementation. I need to design Huffman encoder with standard tables.
  12. R

    Difference between clock and normal buffer, clock driver and clock buffer

    question buffre is used to reduce the delay(isolates two parts)........where as driver, drives the network (for that we need to choose different drive capabilities based on load). Added after 3 minutes: to construct a driver you need to set the transistor sizes and you can find theory on...
  13. R

    Please give me some advise !!!

    if u r sure that u will get placed in vietnam, prefer Altera
  14. R

    Looking for synthesis books that discuss particle approach

    Re: Synthesis Books hi ! u try to go through Design Vision user guide. it is a GUI for synopsys Design Compiler. in that synthesis is explained with an example (RISC core). it will help u. then u go through DC user guide once again.
  15. R

    I want good material on STA

    synopsy prime time documentation would give you fairly good information on STA....SO try to get it........i will try to upload..
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