Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
verification question
In a packet processing ASIC at high data rate packets can be dropped.
For verifying such a ASIC reference model verification approach will not work because modeling this behavior is not possible without having cycle accurate model. So what is the best way to automate...
I want to know what care should be taken while developing a testbench for RTL verification & intended to be used for netlist simulations.?
I am currently avoiding driving on observing signals inside the design...please provide ur tips on this...
cross coverage using psl
i wnat to do cross coverage of two 16 bit vectors but I want to exclude some conditions. Is it possible using psl? please provide me some reference.
thanx
the verification of scheduling algorithms
Can anyone suggest best way to verify scheduling algorithm RTL code.
how can i take care of timing mismatches between the reference model and RTL.
Hi,
1. I am using ISS for random Simulation.
2. all instructions and addressing modes verified with directed testcases.
But I am still not clear how to verify the pipeline in the processor.
Do u guys have any idea on this.
thanx
I want to do verification of CPU core.
I wanted to know if I am using systemC for verification. What could be the best methodology to verify different assembly instructions. If CPU core has pipelined architecture how to validate the output after each instruction in case of random simuations.
thanx
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
