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Recent content by rara801

  1. R

    VHDL code problem design 8bit wide 2-to-1 multiplexer

    but how to crete the buffer command?? i'm still don't get it library ieee; use ieee.std_logic_1164.all; entity part2_2 is PORT( x:IN STD_LOGIC_VECTOR(7 DOWNTO 0); y:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S:IN STD_LOGIC; SW:BUFFER STD_LOGIC_VECTOR(17 DOWNTO 0); LEDR :OUT STD_LOGIC_VECTOR (17...
  2. R

    VHDL code problem design 8bit wide 2-to-1 multiplexer

    ello guys... i'm having a problem with the vhdl coding... this my coding for 8bit wide 2-to-1 multiplexer....i need to connect the switches to red light LEDR and the the output to green light LEDG in de2 board but the problem the interface object "SW" of mode out cannot be read. Change object...

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