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Recent content by ranjbar_7

  1. R

    circuit view of a vhdl code

    hi i need a circuit view of my vhdl code but i dont know how to get to it xilinx ISE gives me a rtl view i need somthing lke this for my vhdl cod
  2. R

    Critical path delay with design compiler

    for finding the critical path delay i have used the report_timing comand in my script and i get ths result but i don't know which data is critical path delay? data arrival time? thanks in advance Startpoint: data_in[0] (input port clocked by vclk) Endpoint: output[1] (output port clocked...
  3. R

    Design compiler libraries

    yes vijay.mani884 i didn't have any experience and i didn't know how to start
  4. R

    Executing a script with design compiler and encountering error

    thank u vijay.mani884 in fact i don't know how to write a script for dc to estimate power and critical path delay
  5. R

    Design compiler syntax error near or at token library

    Thank you very much - - - Updated - - - Thank you very much
  6. R

    Design compiler syntax error near or at token library

    hi when i execute this script i get this error from DC can anyone help me? thanks in advance Error: ./third.vhd:5: Syntax error at or near token 'library'. (VER-294) this is my vhdl code library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity third is Port ( data_in : in...
  7. R

    Executing a script with design compiler and encountering error

    hi I have written this vhdl code and a script for it when i excute this scipt with design compiler i get this errors but befor writing the scrpit i have Synthetized it with xilinx ISE there wasn't any errors! what should i do can anone help me Thanks in advance ---------------- errors: Error...
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    how can i get delay report from design compiler

    Thank you. I'll get right to it! - - - Updated - - - Thank you. I'll get right to it!
  9. R

    how can i get delay report from design compiler

    hi in the scipt that we wrote for design compiler what we should write for geting delay report? i have written this script what should I add to it? -------------------------------------------------------- set my_files second.vhd set my_toplevel project1 set my_clock_pin CLK set...
  10. R

    vhdl programming with xilinx ISE and encountring errors, can anyone help me

    thank you barry
  11. R

    vhdl programming with xilinx ISE and encountring errors, can anyone help me

    hi i have wriiten this simple vhdl code and i expect no error but i get this erros and i don't know why would u please help me thanks in advansce code ----------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity...
  12. R

    Design compiler libraries

    yes unfortunately i have none of them
  13. R

    Design compiler libraries

    i need link library target library symbol library and synthetic library ,and i don't know how to create them from libs thank u
  14. R

    Design compiler libraries

    from my foundry!!! would u please send me a link for download thanks in advance
  15. R

    Design compiler libraries

    hi i need design compiler 60 nm libraries for using design compiler where can i find it?
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