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thanks for the tips.i actually got it to work with an output swing of 2.7 to 3.3 v. and my vref is 2.7 so that seems right. one last question though. i made a two stage opamp (diff to single ended) that takes a sin from 2.7 to 3.3 and shifts it down to a common mode of 1.65. so it is supposed...
hi thanks for the input. so i guess i need to have the pmos load in linear region always and the diode connected pmos should obviously be in saturation. but does that pmos load always have to be linear, because i asked my teacher and she said it can be in saturation as well as it gives a bigger...
hi actually i used the maneatis delay cell instead and got it working at 500mhz with everything in saturation. what is the best way to convert the vco output into a square wave which will go back to the pfd. will a simple comparator, like a opamp, work?
Hi I am designing a vco with replica biasing and have a few questions. For the design, I'm using a differential design as in the picture below. This was taken from Razavi's book. Now to the problems. I can't seem to get the replica bias to work properly, as the Vds value from the pmos in the...
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