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Recent content by ranga

  1. R

    [Problem] clock_gating_cell in SCAN insertion

    By default clk-gating cells are dont toch. you need to set this as remove _attribute dont use
  2. R

    What are the types of routing?

    routing One change Trial route for congestion analysis Wroute ( has got Metal layer restiction)max 5 layers ?? Nano route Yes >for detailed routing
  3. R

    a problem when using dc_shell-t>report_lib

    May be thesearch paths Check
  4. R

    Tcl and Perl for backend VLSI design

    tcl or perl Most of the tools are built on TCL.May be u learn TCL
  5. R

    Environment Variables

    Enironmental mainly are the parameters that are not part of the design but influence the design PVT ,WLM etc
  6. R

    can a latch have setup and hold time violation...

    Good insight into the question which never satisfies anyone
  7. R

    How to calculate minimum skew and proceed with duty cycle other than 50% in STA?

    doubts in sta I just came acrooss will be back
  8. R

    Looking for tutorials to learn using DC2000.05

    Re: [Help] How to learn DC? mailid is ranganadh.m@gmail.com please mail me DC refernce manuals
  9. R

    Full detailed ASIC back-end design flow

    Re: asic design flow There is no particular flow .Showed one is the overall flow. things in it keep changing. I suggest you refer one of the tools userguides(cadence/synopsys)
  10. R

    synopsys design compiler workshop

    Re: primetime workshop lab Primetime materials userguides will be available from solvnet
  11. R

    ASIC Back-End Course in India????

    JOIN CDAC or vedant or vEDA-IIT in HYDERABAD All these have a very good reputation. Else where you simply get robbed. Take a good decision :D
  12. R

    wht are the tools available for DFT?

    Mentor tools are sign-off as now Synopsys tools are a step behind
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