Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Can someone tell me what conformal license I need for low power checks? Is ultra good enough?
I have never done that before so any sight on the file format would help too
Yes you definitely can set 2 environment variable sin one file.
set <VAR1> <value>
set <VAR2> <value>
If you are using perl then $ENV{'VAR1'} is how you call the environment variable.
You can also use system commands in your script or backtick to set env.
For ex : system "setenv VAR1 value"...
Thank you all. I did a vpx report environment and noticed that not all modelling directives were getting set in the flow due to some bug. I was manually able to set the modelling directives, add pin constraints and remodel -seq_constant -repeat followed by analyze setup resolved this issue
$$ means the current process ID. You can find all pre-defined perl variables here https://perldoc.perl.org/perlvar.html or do a "man perlvar" and it should open the help page.
Thanks Sharath. I believe analyze setup should cover most of the modelling directives even if I haven't manually entered them in my do file. So wondering what else could me missing.
Interface signals like input and output ports, DFFs, Dlats, Z/E and cut gates, Bboxes are generally referred to as they key points. Assume you have a huge design and you want to compare RTL vs netlist. You would break the design into smaller cones and then compare. Break where?(At some cut point...
There is already an explanation on aborts above so let me explain a little about the mismatches/non-equivalencies.
95% of non-eqs are due to missing modelling directives. You might have used some commands for netlist optimization or for timing reasons during netlist generation. These will show...
Hi all,
I am comparing RTL vs netlist using conformal and when I do vpx analyze noneq <gate_id> , I get 30+ of these errors(similar ones as below): I have used all modelling directives. Tried set flatten model -seq_constant, remodel -seq_constant -repeat but it seems to be increasing my non-eq...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.