Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thank you guys!!!
Thanks a lot for the reply guys.
I have another basic question.
What are the solutions for reducing the Hot-electron effect?
* increasing the oxide thickness
* LDD structure -- I am not sure how this helps in reducing? if someone can explain it will be helpful.
How...
Basic MOS question
Whats the main reason for using polysilicon instead of Metals for gates?
I remember reading somewhere its because of the alignment problems of source/drain wrt metal? I am not sure self-aligment process available now also have this problem with metals?
Re: Problem with Layout
BULLS EYE !!!!!
That is the exact problem, I didnt realise it (infact I didnt even think in those lines) till you pointed it out. I am using an n-well process and not a twin-tub process. What do you think can be the workaround? Using PMOS instead of NMOS to perform the...
I am trying to implement a sum-product block as shown given in
**broken link removed**
When I did the layout of the whole circuit, and run the LVS check, I get a short circuit between GND, VbxF, VbyF. But looking at the circuit, there is no connection between VbxF and VbyF and GND. I am not...
Re: Help Subthreshold Design
@ Prakash,
The transistors are of dimensions [W=5um, L=0.5um].
I want to know if sizing of the transistors was a solution, then I can as well remove the reference voltages Vbx and Vby isnt it?
@ |IAngel|
The threshold voltage of transistors I am using is in the...
Re: Monte-Carlo
Yes, what you said is correct. But I have to tradeoff between area vs variations in o/p wrt transistor mismatch. As the standard deviation is inversely proportional to square root of (WL).
Help Subthreshold Design
I am having some problem in making the transistors operate in weak inversion. The circuit attached is used as a sum-product block.
All the input currents can range between 0 to 1 uA.
Iy0 + Iy1 <= 1uA
Ix0 + Ix1 <= 1uA
The NMOS transistors M1 to M10 have the dimensions...
Monte-Carlo
I am designing a sum-product circuit (based on gilbert-cell). I have 2 input current vectors X and Y. Z is the output current vector. All the MOS transistors are operated in weak inversion (subthreshold). The paper which I am following says that monte-carlo simulations should be run...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.