Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ranair123

  1. R

    Why is polysilicon used instead of metal for gates in MOS?

    Re: thank you guys!!! -- I guess High K dielectrics might help in increasing the thickness to get the same current level as SiO2??
  2. R

    Why is polysilicon used instead of metal for gates in MOS?

    thank you guys!!! Thanks a lot for the reply guys. I have another basic question. What are the solutions for reducing the Hot-electron effect? * increasing the oxide thickness * LDD structure -- I am not sure how this helps in reducing? if someone can explain it will be helpful. How...
  3. R

    Why is polysilicon used instead of metal for gates in MOS?

    Basic MOS question Whats the main reason for using polysilicon instead of Metals for gates? I remember reading somewhere its because of the alignment problems of source/drain wrt metal? I am not sure self-aligment process available now also have this problem with metals?
  4. R

    Problem with layout and LVS report

    Re: Problem with Layout BULLS EYE !!!!! That is the exact problem, I didnt realise it (infact I didnt even think in those lines) till you pointed it out. I am using an n-well process and not a twin-tub process. What do you think can be the workaround? Using PMOS instead of NMOS to perform the...
  5. R

    Problem with layout and LVS report

    I am trying to implement a sum-product block as shown given in **broken link removed** When I did the layout of the whole circuit, and run the LVS check, I get a short circuit between GND, VbxF, VbyF. But looking at the circuit, there is no connection between VbxF and VbyF and GND. I am not...
  6. R

    [Help] Monte Carlo simulation with pspice

    The tutorial here **broken link removed** explains how to setup the device tolerance.
  7. R

    I need help with subthreshold design

    Re: Help Subthreshold Design @ Prakash, The transistors are of dimensions [W=5um, L=0.5um]. I want to know if sizing of the transistors was a solution, then I can as well remove the reference voltages Vbx and Vby isnt it? @ |IAngel| The threshold voltage of transistors I am using is in the...
  8. R

    How the Monte-Carlo simulations fix the transistors width?

    Re: Monte-Carlo Yes, what you said is correct. But I have to tradeoff between area vs variations in o/p wrt transistor mismatch. As the standard deviation is inversely proportional to square root of (WL).
  9. R

    I need help with subthreshold design

    Help Subthreshold Design I am having some problem in making the transistors operate in weak inversion. The circuit attached is used as a sum-product block. All the input currents can range between 0 to 1 uA. Iy0 + Iy1 <= 1uA Ix0 + Ix1 <= 1uA The NMOS transistors M1 to M10 have the dimensions...
  10. R

    Anyone has a circuit as a sub-threshold example?

    I am currently designing sum-product blocks using gilbert multipliers. All the transistors (except current mirrors) operate in subthreshold region.
  11. R

    How the Monte-Carlo simulations fix the transistors width?

    Monte-Carlo I am designing a sum-product circuit (based on gilbert-cell). I have 2 input current vectors X and Y. Z is the output current vector. All the MOS transistors are operated in weak inversion (subthreshold). The paper which I am following says that monte-carlo simulations should be run...

Part and Inventory Search

Back
Top