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Recent content by ramz

  1. R

    design of 10 bit number controlled oscillator ??????????????

    can any one plz help me in design of above experiment using standard cell approach .. i am using tanner eda tool for this design. plz help me with tthe circuit diagram and its explanation.
  2. R

    will a case statement work inside a for loop ( vhdl)

    case statements in vhdl for i in 0 to 3 loop case(i) when 1 => some statement executed when 2 => when 3 => when others => end case end loop i tried to use like this, but does not work.. any suggestions appreciatedd
  3. R

    for loop help in vhdl.....

    for in vhdl actually i want to know a for loop works... when i wrote a test bench.. the simulation results shown me only the last incremented value of for loop.. actually for any loop say i=0 to 5.. how many clock cycles are requied to perform this Added after 2 minutes: also i would like...
  4. R

    for loop help in vhdl.....

    for loop in vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity...
  5. R

    how to find greatest among 5 inputs in vhdl......

    i am having 5 inputs.... and want to find the greatest among 5.... like arranging numbers in descending order..... can any genius help me out
  6. R

    design of 2D NOC Switch (control logic)

    2d noc Hi... Can anyone help me out in designing a 2D switch...... plz... I am unable to make a control logic for the switch... i am using nostrum protocol
  7. R

    How to divide clock by 5 ?

    Re: Clock Divide by 5 sorry .. i have done mistake ..... if any one could find ans plz reply
  8. R

    What does GDSII stand for ?

    Re: gds graphical design specification information interchange
  9. R

    reg: physical design io file

    soc encounter
  10. R

    How to divide clock by 5 ?

    Re: Clock Divide by 5 if we to divide clk by 5, first divide clk by 4 and then perform and/or operation between original clk and divided/4 clk which gives divide by 5..... i tried and got... if wrong correct.. plz
  11. R

    How to divide clock by 5 ?

    Re: Clock Divide by 5 could any one send attachment for frequency divider using odd numbers 3,5,7 ,....
  12. R

    Unity gain buffer for driving large load capacitance

    Unity gain buffer design a souce follower
  13. R

    why moore is safer then mealy?

    moore is glitch free... where as meelay is sensitive to glitches
  14. R

    reg: physical design io file

    the inputs to physical design tool are netlist, timing libs , io file and sdc file, lef file. i am having doubt how to write an io file. i am unable to understand the concept behind writinof io file. could any body explain in detail of writng of io file
  15. R

    without wire load model

    without using wire load models in our script file ... the synthesis tool will take default wire load and then calculate the estimated delays of the paths.. wire load model is must for synthesis.. if wrong plz correct
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