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Recent content by rampat

  1. R

    3.3V supply opamp design with 1.8V devices

    Erik l,Thanks for your reply .... I missed out provided couple of information...The process has devices which can handle VDS=3.3( drain extended mos) or VGS=3.3( thick oxide).How do use these devices so that either of the junction VDS or VGS should not experience reliability issues especially...
  2. R

    3.3V supply opamp design with 1.8V devices

    Hi All I need to design a opamp with 3.3V supply and only 1.8V devices are available from the process.How to take care of the reliability issues for the devices? If anyone knows solutions or any reference/papers to the above problem it will be a great help. Thanks rampat
  3. R

    bandgap startup problem

    yes it gives proper bandgap voltage at weak,-40 in OP.But when simulate transient with supply ramp,output does not settle to bandgap voltage ? -rampat
  4. R

    bandgap startup problem

    Hi all, Could someone help me with the startup problem in my bandgap circuit? I have startup problem for lower temperatures .i.e if i simulate ckt for weak -40. I get output waveform as attached .. Thanks in advance rampat
  5. R

    [SOLVED] How to use PSS of Cadence Spectre ?

    if it does not converge even after using proper fund.freq and tstab period,you can use initial conditions from the transient settled op as ic for pss... also you can play with steadyratio and tolerances to make pss converge..once pss converges make you sure you got the correct outputs from your...
  6. R

    What will decide the VDS drop of 4 transistors bias in cascode structure?

    Hi All I have one very basic question.if you have 4 transistors (2 pmos 2 nmos) in cascode structure,what will decide the vds drop across each of the transistor assuming all are in saturation ? thanks rampat
  7. R

    What is the acceptable OPA phase margin ?

    Re: about phase margin i feel there is something wrong with simulation setup..Usually we try to measure phasemargin for -ve f/b loop...I assume you are feeding ac signal in the negative feedback loop..so at dc itself output is inverted i.e 180' phaseshift,but you are saying PM=-180' which...
  8. R

    how to determine antialising filter specification?

    it depends upon the bandwidth of the signal you feeding to the ADC.Basically antialias filter used to make input signal bandlimited..if you are sampling signal with fs,you need to figure out what kind of attenuation you want to see for fs components so that they fs components that fold back into...
  9. R

    How to decide BW of error amp,position of Poles

    BW is always decided by settling error but in case of LDO you have to consider pSRR of LDO.
  10. R

    How to choose bjt for a bandgap design?

    Re: how to choose bjt Larger the BJT area and lesser is the mismatch.it is always better to go for more wider BJT's and depending on the maximum junction voltage BJT can see,you can select 1.8V/3.3V BJT device
  11. R

    How to use resPwl component from the AnalogLibrary in Spice/Spectre ?

    Hi All How to use resPwl component from the AnalogLibrary in spice/spectre ? -rampat
  12. R

    crystal oscillator simulation

    Hi Keith, yes I was not running it for long time..I was giving a step of 1V with tr=1us and was running for 10us..and i also observed oscillations dying out even after+ve feedback..But how do I decide the run time and the time step for the simulation? Thanks rampat
  13. R

    crystal oscillator simulation

    I am trying to model crystal oscillator for fs=26MHz.When I apply a step for open loopI can see underdamped oscillation of 26MHz,But once I put the loop in closed loop to get stable oscillation,the circuit is not converging at all which means i am not able to see sustained oscillation of...
  14. R

    op amp design --help needed

    Hi All, I have opamp spec as follows Adc=100dB,UGB=900MHz,Supply=1.2V ,Tech=0.13u CMOS I have 1.2V MOS devices with vthn=vthp~0.45V Could someone help me in deciding the architecture for above specs ? thanks
  15. R

    adc spec in 10GbE ethernet

    Hi all, what is the kind of adc (specs) used in 10GbE ethernet chip.and how do you arrive at the specs for adc in 10GbE ethernet applications ? thanks rampat Added after 38 minutes: and another basic doubt,is there adc block in ethernet chip ? -rampat
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