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Hi,
I am trying to work out a LOG10 module in verilog by the tutorial
https://www.mikrocontroller.net/attachment/31117/cordic1.pdf
so far so good, i got this module working and pipelined, and the error is <0.002.
BUT, there is a restriction by this algorithm, that is:
according to the...
Hi Scanman,
Thank you!:D
well, use a counter to count system clock is a great idea for a high speed system clk.
The problem is, the system clock is only 20Mhz and can't be modified, and I set the AD7490 to be 10Mhz.
as on the datasheet it says the delay is 14~20ns, so how can i do now? I...
Hi everyone,
i am currently writing a FPGA interface module to AD7490 and I get stuck on the 'first bit' reading problem at DOUT.
the problem is, there is an interval between holding down the CS and the first bit of DOUT comes out. this makes i can't get the DOUT data correctly.
so how can i...
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