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Recent content by Ramesh Reddy

  1. Ramesh Reddy

    VERIFICATION METHODOLOGY

    Hi, In Reference Verification Methodology (RVM) Which Uses VERA as language has Smart Queues which can be resized at any pint of time Some times In such a situation, size() is likely to be a large integer value which creates a very large random SmartQ that will require a lot of simulation...
  2. Ramesh Reddy

    VHDL book for Beginners

    Hi, All the above mentioned book's good.. But specifically i recommend u as beginner it's really nice 2 study a book by -PEDRONI
  3. Ramesh Reddy

    Who is Market Leader in FPGA - ALTERA or XILINX

    Hi No doubt it's XILINX only, coz i find lot of good facilities like darg n drop and exchange of slices etc... Regards, Reddy.PSR
  4. Ramesh Reddy

    What is the best VHDL book?

    vhdl solution navabi Hi As per my knowledge Circuit Design with VHDL by Volnei A. Pedroni is the very good book for beginers dougls Smith and ashendun is better 2 improve all the designning skills regards, Reddy.PR
  5. Ramesh Reddy

    Help me write an cuncurrent assertion statement in VHDL

    Hi can u solve my question 1)Write an cuncurrent assertion statement that ensures a signal STATE never has the enumeration literals TWO_ONE and THREE_ONE Thanks&Regards' Reddy.PR
  6. Ramesh Reddy

    info abt pci express module

    Hi all I'm interested in doing my project on PCI, can u plz suggest me which module is better in point of time taking(hardly i have 1 month to complete) and also in point of ncie sorce code(in any HDL language)
  7. Ramesh Reddy

    Gate and Transistor Drawing tool

    hi kef if u hav knowledge of spice it's much better then ORCAD of cource in ORCAD is also having verg good fecilities now a days that depends on you... Added after 41 seconds: hi kef if u hav knowledge of spice it's much better then ORCAD of cource in ORCAD is also having verg good...
  8. Ramesh Reddy

    Query in multiple clockdomain

    Hi all, Whenever there is going to be transactions b/w 2 clock domain, irrespective of the clock's speed you need to synchronize them. Here synchronizer is needed to avaoid the metastable states in the machine, which can be caused due to 2 different clcok-tree's flop's direct talking ...
  9. Ramesh Reddy

    what r the pros n cons b/w "SystemC" and "Sys

    Hi, I'm very much interested to know which is better whether System C or System verilog can u any body suggest on this ok thank's to all
  10. Ramesh Reddy

    Synopsys & Cadence tutorial

    Hi, well in ASIC designing it's healthy job doing any thing just by knowing MAGIC and B-Spice in ASIC design taking EDIF netlist into consideration everything follows for a pertyicular design Added after 38 seconds: Hi, well in ASIC designing it's healthy job doing any thing just...
  11. Ramesh Reddy

    any info abt PCI Express Project

    Hi all, Currently i'm doing PG diploma course in VLSI, i just want to do my project on PCI Express. can any body suggest me which module is better and is there any good sites so that i can get any relevant info abt PCI Express Thanking U, Ramesh Reddy.
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